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| STY30NK90Z N-CHANNEL 900V - 0.21 - 26A Max247 Zener-Protected SuperMESHTM MOSFET Table 1: General Features TYPE STY30NK90Z s s s s s s Figure 1: Package ID 28 A Pw 500 W VDSS 900 V RDS(on) < 0.26 TYPICAL RDS(on) = 0.25 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY 2 1 3 Max247 DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products. Figure 2: Internal Schematic Diagram APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR WELDING EQUIPMENT s Table 2: Order Codes SALES TYPE STY30NK90Z MARKING Y30NK90Z PACKAGE Max247 PACKAGING TUBE Rev.3 January 2005 1/10 STY30NK90Z Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) VISO Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Insulation Withstand Voltage (AC-RMS) from All Four Terminals to External Heatsink Operating Junction Temperature Storage Temperature Value 900 900 30 26 16 104 450 3.57 6 4.5 2500 Unit V V V A A A W W/C KV V/ns V - 65 to 150 C ( ) Pulse width limited by safe operating area (1) ISD 26A, di/dt 400A/s, VDD V(BR)DSS, Tj TJMAX. (*) Limited only by maximum temperature allowed Table 4: Thermal Data Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.277 30 300 C/W C/W C Table 5: Avalanche Characteristics Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, I D = IAR, VDD = 35 V) Max Value 26 500 Unit A mJ Table 6: GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 2/10 STY30NK90Z ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, T C = 125 C VGS = 20V VDS = VGS, ID = 150 A VGS = 10V, ID = 14 A 3 3.75 0.21 Min. 900 10 100 100 4.5 0.26 Typ. Max. Unit V A A A V Table 8: Dynamic Symbol g fs (1) Ciss Coss Crss C oss eq. (3) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 14 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 26 12000 852 166 377 67 59 250 72 350 51 190 490 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC VGS = 0V, VDS = 0V to 720 V VDD = 450 V, ID = 13 A RG = 4.7 VGS = 10 V (see Figure 17) VDD = 720 V, ID = 26 A, VGS = 10V (see Figure 20) Table 9: Source Drain Diode Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 28 A, VGS = 0 ISD = 26 A, di/dt = 100 A/s VDD = 100 V, Tj = 25C (see Figure 18) ISD = 26 A, di/dt = 100 A/s VDD = 100 V, Tj = 150C (see Figure 18) 1 18.9 36.6 1.33 25.2 37.8 Test Conditions Min. Typ. Max. 28 112 2 Unit A A V s C A s C A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. 3/10 STY30NK90Z Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STY30NK90Z Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STY30NK90Z Figure 15: Avalanche Energy vs Starting Tj 6/10 STY30NK90Z Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/10 STY30NK90Z Max247 MECHANICAL DATA mm MIN. A A1 b b1 b2 c D e E L L1 4.70 2.20 1.00 2.00 3.00 0.40 19.70 5.35 15.30 14.20 3.70 TYP. MAX. 5.30 2.60 1.40 2.40 3.40 0.80 20.30 5.55 15.90 15.20 4.30 MIN. inch TYP. MAX. DIM. P025Q 8/10 STY30NK90Z Table 10: Revision History Date 16-Jul-04 23-Mar-04 21-Jan-05 Revision 1 2 3 First Release. Data updated Final Datasheet Description of Changes 9/10 STY30NK90Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10 |
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